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| • | MIPS32® M4K® 32-bit core with 5-stage pipeline |
| • | 80 MHz maximum frequency |
| • | 1.56 DMIPS/MHz (Dhrystone 2.1) performance at zero Wait state Flash access |
| • | Single-cycle multiply and high-performance divide unit |
| • | MIPS16e® mode for up to 40% smaller code size |
| • | Two sets of 32 core register files (32-bit) to reduce interrupt latency . |
| • | Prefetch Cache module to speed execution from Flash |
| • | Operating voltage range of 2.3V to 3.6V . |
| • | 64K to 512K Flash memory (plus an additional 12 KBof Boot Flash) |
| • | 16K to 128K SRAM memory |
| • | Pin-compatible with most PIC24/dsPIC® DSC devices . |
| • | Multiple power management modes |
| • | Multiple interrupt vectors with individually programmable priority . |
| • | Fail-Safe Clock Monitor mode |
| • | Configurable Watchdog Timer with on-chip Low-Power RC oscillator for reliable operation . |
| • | Atomic SET, CLEAR and INVERT operation on select peripheral registers . |
| • | Up to 8-channels of hardware DMA with automatic data size detection . |
| • | USB 2.0-compliant full-speed device and On-The-Go (OTG) controller: - Dedicated DMA channels |
| • | 10/100 Mbps Ethernet MAC with MII and RMII interface: - Dedicated DMA channels |
| • | CAN module: - 2.0B Active with DeviceNet™ addressing support - Dedicated DMA channels |
| • | 3 MHz to 25 MHz crystal oscillator |
