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| • | Modified Harvard Architecture |
| • | Up to 16 MIPS Operation @ 32 MHz |
| • | 8 MHz Internal Oscillator with 4x PLL Option andMultiple Divide Options |
| • | 17-Bit x 17-Bit Single-Cycle Hardware Multiplier |
| • | 32-Bit by 16-Bit Hardware Divider |
| • | 16 x 16-Bit Working Register Array |
| • | C Compiler Optimized Instruction Set Architecture: - 76 base instructions - Flexible addressing modes |
| • | Two Address Generation Units for Separate Read and Write Addressing of Data Memory |
| • | Operating Voltage Range of 2.0V to 3.6V |
| • | Flash Program Memory: - 1000 erase/write cycles - 20-year data retention minimum |
| • | Self-Reprogrammable under Software Control |
| • | Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes |
| • | On-Chip 2.5V Regulator |
| • | TAG Boundary Scan and Programming Support |
| • | Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) |
| • | Flexible Watchdog Timer (WDT) with On-Chip,Low-Power RC Oscillator for Reliable Operation |
| • | In-Circuit Serial Programming. (ICSP.) and In-Circuit Emulation (ICE) via 2 Pins |
| • | Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip,low-power RC oscillator |
